ASIC front-end verification engineer
Core
Architect and develop block-level verification environments for ASICs using SystemVerilog and UVM, verify large blocks independently, and sign off designs for tape-out.
Role type
ASIC front-end verification engineer
Builds
ASIC verification suites and test environments for complex integrated circuits
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC verification, SystemVerilog, UVM methodology, constrained-random verification, Perl/Tcl scripting, ASIC debugging, functional coverage analysis, gate-level simulation
Preferred skills
OVM/VMM methodology, Ethernet protocol verification, Python/shell scripting for verification infrastructure
Technologies
SystemVerilog, UVM, VCS, NC, Perl, Tcl, Python, Shell
Responsibilities
Architect and develop block level verification environments for sub-system and fullchip; Define, architect, code, and deliver verification suites/tests for ASICs; Verify large ASIC blocks independently and sign off them for tape-out; Work closely with logic designers to resolve bugs; Develop scripts to improve verification infrastructure
Seniority
Mid-level IC engineer
