Principal Physical Design Engineer
Core
Implement physical design for large SoC chips from RTL to GDSII, managing IP integration, floorplanning, place & route, and sign-off verification.
Role type
Principal Physical Design Engineer (SoC)
Builds
Large System-on-Chip (SoC) designs ready for manufacturing tapeout
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC physical design, IP integration, floorplanning, place & route, clock network development, power grid design, static timing analysis, DRC/LVS/ERC verification, Linux shell scripting (Perl/TCL/Python), 2.5D/3D packaging knowledge
Preferred skills
2.5D/3D packaging, high-performance chip design, DFT integration
Technologies
RTL, GDSII, Verilog, Linux, Perl, TCL, Python
Responsibilities
Implement physical design at large SoC level from RTL to GDSII; Integrate IP blocks and sub-chips; Build full chip floorplan including bump placement and power grid; Develop chip-level clock networks; Optimize timing, area, and power constraints; Run physical design verification flow to fix violations; Collaborate with architecture, DV, and package teams for tapeout.
Seniority
Principal, hands-on IC
