Product Engineer I - II or Sr. Product Engineer, Texas Institute for Electronics
Core
Validating and optimizing IC & test structures for 3D heterogeneous integration (3DHI) semiconductor packaging to improve yield, performance, and reliability.
Role type
Product Engineer (IC & Test Structure Validation & Optimization)
Builds
2.5D/3D advanced packaging solutions and semiconductor manufacturing equipment
Domain
Semiconductor manufacturing / Advanced packaging / Defense electronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor device physics, Mixed signal IC behaviors, Python/MATLAB/C/C++/Perl programming, Failure analysis, DOE design, Data analytics, Multi-physics characterization
Preferred skills
Master's or PhD in semiconductor engineering, IC/Micro-system Design, Wafer fab Integration, Semiconductor Packaging manufacturing
Technologies
2.5D/3D packaging, 3D-ADK, ATE, Python, MATLAB, C/C++, Perl
Responsibilities
Product and test vehicle validation to specifications, Develop and support TIE's 3D-ADK, Interpret fab metrology and E-test yield data, Drive corrective actions for yield and reliability issues, Collaborate with design teams on package compatibility, Define product DFT & DFM requirements, Bench/lab validation of IC solutions, Leverage data analytics for yield optimization, Own entire product life cycle from bring up to customer qualification, Collaborate with customers to resolve field failures
Seniority
Entry to Senior level (0 to 10+ years experience)
