Layout/Mask Designer
Core
Develops and implements physical design solutions for System-on-Chip (SoC) devices from RTL, netlists, and design constraints.
Role type
Senior IC physical design engineer (SoC)
Builds
System-on-Chip (SoC) devices
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
floor planning, power grid design, placement, clock tree synthesis, routing, timing closure, physical verification, design quality analysis, implementation flow validation
Preferred skills
EDA tools, automation scripts
Technologies
EDA tools, automation scripts
Responsibilities
Develops and implements physical design solutions for SoC devices; Performs floor planning, power grid design, placement, clock tree synthesis, routing, timing closure, and physical verification; Analyses design quality and verifies layouts meet performance, power, area, and manufacturability requirements; Supports tape out activities.