Design for Test Engineer
Core
Implementing Design for Test (DFT) strategies for 3nm and 5nm networking chips, including IP-level DFT, scan insertion, ATPG pattern generation, and MBIST verification. (via careerplan.io/jobs/g758e812-design-for-test-engineer-at-arrow-electronics-inc)
Role type
Senior IC Design for Test Engineer
Builds
Production silicon for networking chips and related IPs (PLL, SerDes)
Domain
Semiconductor / Networking / SoC Design
Required skills
Scan insertion, ATPG, GLS, pattern simulation, MBIST insertion, IEEE 1149.1 JTAG, RTL checking, Perl scripting, Shell scripting, TCL scripting
Preferred skills
Multi-million-gate SoC experience, low-power DFT knowledge, Mentor Tessent toolset familiarity
Technologies
Mentor Tessent, Synopsys Spyglass, Synopsys Tetramax, Cadence Modus, VCS, Verdi, DAeRT
Responsibilities
Perform RTL checks for scan-insertion readiness; execute scan insertion with Tessent TestKompress; generate ATPG patterns in compressed and uncompressed modes; run pattern simulations with and without timing across multiple corners; debug mismatches; write automation scripts in Perl, Shell, and TCL; enhance DFT flows via DAeRT and Makefile improvements; perform MBIST insertion and verification at block and top levels; support silicon debug and bring-up; insert and verify IEEE 1149.1 JTAG functionality.
Seniority
Senior, hands-on IC
