PD Engineer, Annapurna Labs
Core
Lead block physical implementation and optimize RTL-to-GDS flows for high-performance machine learning inference hardware.
Role type
Senior Physical Design Engineer (ASIC/SoC)
Builds
Cloud-scale ML inference chips (e.g., AWS Inferentia)
Domain
Semiconductor hardware design / Machine Learning Infrastructure
Deliverable
production ML models | product features
Required skills
block design, synthesis, floor planning, place and route, timing closure, IR drop analysis, physical verification, EDA tool proficiency (Cadence, Synopsys, Mentor Graphics), RTL-to-GDS flow optimization, QoR metrics analysis
Preferred skills
IP integration, design parameter extraction, trend analysis, EDA tool vendor partnership
Technologies
Cadence, Synopsys, Mentor Graphics, AWS Cloud
Responsibilities
Lead block physical implementation through synthesis, floor planning, place and route, and sign-off activities. Develop cloud infrastructure supporting physical design work. Improve RTL-to-GDS flows and methodology to strengthen PPA and turnaround time. Build dashboards and reporting tools to track projects and visualize QoR. Partner with EDA tool vendors to evaluate new tools and resolve defects.
Seniority
Senior, hands-on IC
