Silicon Design-for-Test (DFT) Engineer
Core
Design and implement Design-for-Test (DFT) solutions for high-performance silicon used in AGI compute platforms, covering compute, memory, and high-speed connectivity.
Role type
Silicon DFT Engineer
Builds
Best-in-class silicon for high-performance and sustainable GenAI workloads
Domain
Semiconductor / Hardware / AGI Compute
Deliverable
production ML models | product features
Required skills
DFT implementation (MBIST, at-speed scan, scan compression), JTAG/IEEE 1149.1, IJTAG/IEEE 1687, Streaming Scan Networks (SSN), PHY firmware loading/validation (SPI/I2C/JTAG), PHY DFT interface integration, EDA tools (Synopsys DFT Compiler, Mentor Tessent)
Preferred skills
System-level DFT access, hierarchical test access, test data compression, multi-die/chiplet DFT
Technologies
Synopsys DFT Compiler, Mentor Tessent, SPI, I2C, JTAG, IEEE 1149.1, IEEE 1687
Responsibilities
Design functional test solutions for SERDES PHY (loopback, eye diagram, margin testing); Integrate PHY IP blocks with boundary scan and BIST; Develop firmware loading flows for PHY bring-up; Collaborate on silicon test program development from simulation to ATE; Execute DFT implementation and verification flows (scan chain closure, ATPG); Support test escapes root cause analysis
Seniority
Mid to Senior, hands-on IC
