ASIC Package SI/PI Engineer
Core
Drive electrical architecture, modeling, optimization, and validation for advanced AI/HPC silicon and package design, focusing on high-speed SerDes and memory channel architecture.
Role type
Senior IC ASIC Package Signal Integrity / Power Integrity Engineer
Builds
AI-native silicon and tightly integrated systems for OpenAI's supercomputing platform
Domain
Semiconductor / AI Hardware / High-Speed Interconnects
Deliverable
production ML models | product features
Required skills
High-speed channel and PDN analysis, 2.5D/3D package SI/PI, substrate to package co-design, electromagnetic modeling, simulation-to-measurement correlation, transmission-line behavior, impedance, loss, crosstalk, return paths, inductance, decoupling, voltage droop, current distribution
Preferred skills
Advanced 2.5D/3D packaging, silicon or organic interposers, HBM integration, IVR integration, high-speed laboratory validation (VNA, TDR/TDT), package and PCB material properties
Technologies
Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI/PowerDC, Cadence APD/SIP
Responsibilities
Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility through production; Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet interfaces; Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers; Define and optimize package stack-ups, transmission-line structures, via transitions, and bump maps; Develop channel loss, crosstalk, impedance, skew, and link-budget requirements; Perform package-level PDN analysis including impedance, loop inductance, DCIR, and dynamic voltage droop; Drive die/package co-design including bump/BGA assignment and high-speed I/O placement
Seniority
Senior, hands-on IC
