Senior Package Layout Engineer
Core
Develop multi-layer substrate and carrier layouts for 2D, 2.5D, and 3D IC configurations and wafer-level interconnects using redistribution layers.
Role type
Senior IC package layout engineer
Builds
High-speed semiconductor packages and PCBs for consumer connectivity and datacenter products
Domain
Semiconductor / Signal Integrity
Required skills
high-speed layout, electronic design, EDA tools, PCB layout, thermal design, optical design, RF/analog/digital circuits
Preferred skills
Cadence APD, Allegro, AI design acceleration, mechatronics/photonics/electronics manufacturing knowledge, chip-on-board/wirebond/flip-chip/optical assembly, JEDEC/IPC standards
Technologies
Cadence APD, Allegro, EDA tools
Responsibilities
Perform package design feasibility assessments, develop multi-layer substrate and carrier layouts, develop wafer-level interconnect layouts
Seniority
Senior, hands-on IC
