Senior Design/Verification Engineer
Core
Senior IC verification engineer developing advanced digital subsystems within mixed-signal ICs for data communications and video broadcast.
Role type
Senior IC verification engineer (mixed-signal/digital)
Builds
High-performance mixed-signal ICs for data communications and video broadcast
Domain
Semiconductor / Mixed-signal IC design
Deliverable
production ML models | product features
Required skills
Constrained random verification (UVM/OVM/AVM/VMM), SystemVerilog, Python/TCL/Perl/C, behavioral modeling, mixed-level simulation, project planning, technical documentation, mentoring
Preferred skills
None explicitly stated
Technologies
UVM, OVM, AVM, VMM, SystemVerilog, Python, TCL, Perl, C, Linux/Unix
Responsibilities
Functional verification of high-speed digital circuits using constrained random methodology; Behavioral modeling of analog circuits and mixed-level simulation; Create product and technical documents; Prepare project plans and schedules; Provide technical guidance on verification tasks; Collaborate with analog, system, and marketing engineers; Support validation and qualification of end products; Provide leadership and mentoring to other engineers; Continual improvement of verification methodology
Seniority
Senior, hands-on IC engineer with mentoring responsibilities
