Digital Design Verification Trainee
Core
Functional verification of high-speed digital circuits and behavioral modeling of analog/mixed-signal circuits within mixed-signal ICs for data communications and video broadcast.
Role type
Digital Design Verification Trainee
Builds
Mixed-signal ICs for data communications and video broadcast
Domain
Semiconductor / Signal Integrity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Constrained random verification (UVM/OVM/AVM/VMM), SystemVerilog, Python/TCL/Perl/C, Unix/Linux, digital verification methods
Preferred skills
Object-oriented programming, analog circuit modeling
Technologies
UVM, OVM, AVM, VMM, SystemVerilog, Python, TCL, Perl, C, Linux
Responsibilities
Functional verification of high-speed digital circuits using constrained random methodology, Behavioral modeling of analog circuits and mixed-level simulation, Create product and technical documents, Prepare project plans and schedules, Provide technical guidance of verification tasks, Work with analog/firmware/system engineers to ensure design meets requirements, Support validation and qualification of end product, Provide leadership and mentoring to other engineers, Continual improvement of design verification methodology
Seniority
Trainee, entry-level IC design