Analog Mixed-Signal IC Design Engineer (Custom Digital Timing Characterization and Liberty Modeling) – TeraWave
Core
Develop, simulate, characterize, and deliver Liberty (.lib) timing models for custom analog-digital interface circuits used in complex integrated circuits.
Role type
Senior Mixed-Signal / Custom Digital IC Designer (Library Characterization)
Builds
High-quality Liberty timing models and related collateral for custom digital and mixed-signal interface blocks
Domain
Semiconductor IC Design (Analog/Mixed-Signal & Custom Digital Timing)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Liberty timing models)
Required skills
Transistor-level circuit design, SPICE simulation, Liberty (.lib) modeling, Static Timing Analysis (STA), PVT corner analysis, Python/Tcl/Perl scripting, CMOS digital circuit design, Waveform analysis
Preferred skills
Cadence Virtuoso/ADE/Spectre, Synopsys PrimeTime/Tempus, extracted-netlist simulation (DSPF/SPEF), Verilog/Verilog-A/SystemVerilog modeling, Reliability analysis (Aging/EM/IR/Monte Carlo)
Technologies
Spectre, HSPICE, Eldo, FineSim, XA, PrimeTime, Tempus, Innovus, Fusion Compiler, Python, Tcl, Perl, SKILL, DSPF, SPEF
Responsibilities
Generate and maintain Liberty .lib models for custom interface circuits; Characterize timing arcs (setup, hold, clock-to-Q, recovery/removal, pulse-width) over PVT corners; Build and debug transistor-level simulation testbenches; Validate .lib files against simulation results and STA behavior; Create automated characterization flows using scripting; Mentor junior engineers in timing characterization
Seniority
Senior, hands-on IC