Senior Design Verification Engineer - TeraWave
Core
Senior Verification Engineer defining strategy and building AI-enabled verification infrastructure for TeraWave's first in-house silicon program (high-throughput modem and DSP-intensive digital beamformer).
Role type
Senior IC ASIC & SoC verification engineer
Builds
Verification environments, reference models, scoreboards, CI systems, and AI-assisted verification platforms for TeraWave satellite communications chips.
Domain
Space-based communications, wireless, modem, baseband, and DSP hardware verification
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, formal methods, constrained-random simulation, metric-driven verification, functional coverage closure, RTL/system-level debug, verification planning
Preferred skills
Wireless/modem/baseband/DSP verification, LDPC/FEC/framing/beamforming logic, formal verification on production silicon, NoC/interconnect verification, fault tolerance/reliability features, C-based stimulus generation, AI/ML/LLM tooling for verification
Technologies
SystemVerilog, UVM, LLMs, AI/ML tools
Responsibilities
Own verification planning and execution for complex blocks; translate specs into strategies and coverage goals; select verification methods; develop environments and assertions; drive coverage closure and regression health; build verification infrastructure and CI systems; apply AI-assisted capabilities; mentor junior engineers
Seniority
Senior, hands-on IC with strategy definition
