Design Engineer II
Core
Design and lead verification infrastructure for processor architectures using simulation and formal methods.
Role type
Senior IC verification engineer (processor architecture)
Builds
Reusable UVM environments, formal verification flows, and AI-driven coverage analysis for RISC-V/ARM processors
Domain
Semiconductor / CPU Design / Verification
Required skills
SystemVerilog, UVM, C/C++, RTL design, Perl, Python, Tcl, AMBA, PCIe, RISC-V, ARM, pipeline verification, memory subsystem verification
Preferred skills
null
Technologies
UVM, SystemVerilog, C/C++, Perl, Python, Tcl, RISC-V, ARM, AMBA, PCIe
Responsibilities
Develop simulation testbenches in C/C++/RTL and lead reusable UVM environment creation; Champion integration of formal verification and AI-driven coverage analysis; Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements; Verify complex pipelines, memory subsystems, or ISA implementations.
Seniority
Mid-level, hands-on IC
