Lead Design Engineer
Core
Define the strategic vision and infrastructure for verification of next-generation Tensilica advanced CPU cores and configurable processors.
Role type
Senior technical leadership DV Architect
Builds
Verification infrastructure and methodologies for complex instruction set architectures (ISA)
Domain
Semiconductor / CPU Design / Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, C/C++, RTL, formal verification, AI-driven coverage analysis, processor integration (RISC-V, ARM), AMBA/PCIe protocols, scripting (Perl, Python, Tcl), SoC/CPU/DSP verification
Preferred skills
null
Technologies
SystemVerilog, UVM, C, C++, Perl, Python, Tcl, RISC-V, ARM, AMBA, PCIe
Responsibilities
Define long-term DV architecture focusing on scalability across processor variants; Architect simulation testbenches in C/C++/RTL and lead development of reusable UVM environments; Champion integration of formal verification and AI-driven coverage analysis; Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements; Provide technical direction and set standards for quality and metric-driven verification across global teams
Seniority
Senior, technical leadership
