RISCV Infra System IP DV - Sr Lead Engineer
Core
Lead engineer for design verification of RISC-V infrastructure systems and IP, developing test plans, debugging, and ensuring functional coverage.
Role type
Senior IC design verification engineer (RISC-V/ARM)
Builds
RISC-V and ARM-based system IP and subsystems
Domain
Semiconductor hardware design verification
Required skills
UVM, System Verilog, functional coverage, code coverage, bus protocols (CHI/AHB/AXI/ACE), multi-core CPU architecture, memory management, virtualization, regression debugging
Preferred skills
Post-silicon bring-up, HW-SW debug, Gen AI, Python/Perl scripting
Technologies
UVM, System Verilog, Python, Perl, CoreSight
Responsibilities
Develop test plans and test cases to cover design feature sets; Debug regression signatures and identify bug fixes; Collaborate with system architects and design teams on failure debugs and coverage closure; Work with emulation teams on code/functional coverage closure.
Seniority
Senior, hands-on IC
