Lead Design Engineer ( Synthesis/LEC/CLP )
Core
Lead Design Engineer executing Synthesis, LEC, CLP, and power-intent flows for advanced ASIC/SoC designs.
Role type
Senior IC physical design engineer (synthesis/verification)
Builds
ASIC/SoC chips for consumer, hyperscale computing, 5G, automotive, aerospace, and health applications
Domain
Semiconductor design automation (EDA)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC synthesis, LEC, CLP flows, UPF/CPF power intent, Tcl/Perl/Python scripting, Unix/Linux, digital design fundamentals, STA basics, low-power architecture
Preferred skills
Debugging synthesis/LEC issues, constraint management, ECO script writing, cross-functional collaboration
Technologies
Cadence Genus, Cadence Conformal, IEEE 1801
Responsibilities
Run and debug LEC sign-off on design blocks; investigate and resolve NEQs and constraint mismatches; Work on Genus synthesis runs to improve QoR, debug SDC/constraint issues; Support CLP flows; Write and maintain ECO scripts and timing/power constraints for design blocks; Independently triage and document issues, escalating complex or systemic issues as needed; Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure; Prepare clear status updates and technical summaries for internal tracking
Seniority
Senior, hands-on IC
