High Performance DSP core Implementation(Synthesis) Senior Lead Engineer
Core
Senior Lead Engineer responsible for Physical Synthesis, timing closure, and low-power implementation of high-performance ASICs and SoCs.
Role type
Senior Lead IC Physical Design Engineer (Synthesis)
Builds
High-performance, low-power ASIC blocks and System-on-Chip (SoC) IP
Domain
Semiconductor / VLSI / ASIC Design
Required skills
Physical Synthesis, Timing Closure, Multi-clock domain design, Low-power design (UPF), Scripting (Python/Tcl/Perl), Equivalence Checking, ECO handling
Preferred skills
MCMM synthesis, Fusion Compiler/Genus tools, LEC/LP signoff tools, Version Control, Regression testing
Technologies
Fusion Compiler, Genus, UPF, Verilog, VHDL, Python, Tcl, Perl
Responsibilities
Write timing constraints for synthesis and STA, perform timing closure for multi-clock domain designs, optimize designs using MCMM and clock gating, handle ECOs and formal verification, collaborate with design/DFT/PD teams for netlist delivery
Seniority
Senior, hands-on IC
