High Performance DSP core Implementation(Synthesis) Senior Engineer
Core
Senior ASIC engineer responsible for physical synthesis, timing closure, and low-power implementation of high-performance digital SoC blocks.
Role type
Senior IC physical design engineer (synthesis)
Builds
High-performance, low-power ASIC blocks and SoC IP
Domain
Semiconductor / VLSI Design
Required skills
Physical Synthesis, Timing Closure, Multi-clock domain design, Low-power design (UPF), Scripting (Python/Tcl/Perl), Equivalence Checking, ECO handling
Preferred skills
MCMM synthesis, LEC, LP signoff tools, Version Control, Regression testing
Technologies
Fusion Compiler, Genus, UPF, Verilog, VHDL
Responsibilities
Write timing constraints for synthesis and STA, perform timing closure for multi-clock domain designs, optimize designs using MCMM and clock gating, handle ECOs and formal verification, collaborate with design and DFT teams for netlist delivery.
Seniority
Senior, hands-on IC
