Product Engineer II
Core
Validating, improving, and regressing functionality of Cadence's Tempus signoff ECO solution to ensure high quality.
Role type
Product Engineer (Physical Design & Timing Signoff)
Builds
Tempus signoff ECO solution for electronic design automation
Domain
Semiconductor / Electronic Design Automation (EDA)
Deliverable
production ML models | product features
Required skills
Static Timing Analysis, Signal Integrity, Delay calculation, timing constraints, Verilog, Physical Design Implementation (Innovus), Scripting (Perl, TCL, Python, C Shell), Timing and power closure with ECO, Front-end/back-end design flow knowledge, QA practices
Preferred skills
Timing sign off solution experience at block or full chip level
Technologies
Innovus, Perl, TCL, Python, C Shell, Verilog
Responsibilities
Define product specifications and release plans, develop product flows to improve quality and performance, define test methodologies, automate processes for system efficiency, work with R&D and product teams to address customer needs
Seniority
Mid-level IC
