Design Engineer II
Core
Frontend Design Engineer developing high-performance physical IP for industry-standard protocols including Consumer PHYs.
Role type
Senior IC digital design engineer (physical IP)
Builds
High-performance physical IP blocks (eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA) for chips, boards, and systems
Domain
Semiconductor / Electronic Design Automation / High-speed serial interfaces
Deliverable
production ML models | product features
Required skills
RTL design, synthesis, constraint generation, power management, DFT, low-power design, FPGA testing, System Verilog, knowledge of USB/PCIe/Ethernet standards, analog mixed-signal basics
Preferred skills
High-speed serial interface link IP experience in advanced nodes, Python/C/C++ programming, Cadence ASIC design tools
Responsibilities
Implement RTL for high-performance Consumer PHYs, define coverage points and testing strategies with verification teams, collaborate with cross-functional teams (Analog, Layout, Backend, Firmware) to complete IP deliverables, integrate IPs into subsystems for customer releases
Seniority
Mid-level IC engineer
