Senior Software Engineer - Low Power Verification
Core
Develop and improve low-power verification software for Palladium and Protium emulation and prototyping platforms, focusing on UPF waveform generation and AI-assisted debug tools.
Role type
Senior Software Engineer (Low Power Verification)
Builds
UPF waveform generation flows (PPC, MC, Dielets) and AI-integrated debug tools for emulation platforms
Domain
Semiconductor EDA / Low Power Verification
Deliverable
production ML models | product features
Required skills
IEEE 1801 UPF, RTL languages (Verilog, SystemVerilog, VHDL), C++ (OO design), debugging (logs, waveforms, traces), scripting (Perl, Tcl/Tk, Python), AI-assisted coding tools
Preferred skills
AI-assisted coding tools (Copilot, Claude, Cursor)
Technologies
UPF, Verilog, SystemVerilog, VHDL, C++, Perl, Tcl/Tk, Python, Palladium, Protium, PPC, MC, Dielets, SAGE, Verisium
Responsibilities
Improve performance and correctness of UPF waveform generation across PPC and MC flows; Improve SAGE-based UPF debug with Verisium; Develop AI-assisted UPF debug tools; Deploy UPF solutions across key flows; Consolidate and unify UPF debug across platforms
Seniority
Senior, hands-on IC
