Lead Verification Engineer
Core
Lead Verification Engineer responsible for product validation of Palladium emulation technologies, including UPF, ensuring quality of releases and features.
Role type
Senior IC verification engineer (emulation/UPF)
Builds
Palladium emulation technology features and releases
Domain
Electronic Design Automation (EDA), Emulation, UPF
Deliverable
production ML models | product features
Required skills
HDLs (Verilog, VHDL), SystemVerilog, C++, UVM, Functional Verification of complex digital systems (SoC), EDA tools (Cadence/Palladium), Debugging design/verification problems, Process automation with scripting
Preferred skills
Prior experience in Emulation/UPF, Mentorship of junior team members, Improvement of verification flows
Technologies
Palladium, UPF, Cadence, SystemVerilog, UVM, Verilog, VHDL, C++, EDA tools
Responsibilities
Verify upcoming features in Palladium, Manage current set of regressions, Participate in Functional Specification and Testplan reviews, Review and guide team members on technical deliverables, Ensure quality of releases and features, Mentor juniors, Contribute to improvement of verification flows
Seniority
Senior, hands-on IC with mentorship responsibilities
