Lead Verification Engineer
Core
Validate AI-generated verification artifacts (UVM, SVA, coverage) and debug customer verification challenges to ensure alignment with industry-standard semiconductor workflows.
Role type
Senior IC verification engineer (AI/EDA focus)
Builds
Ground-truth datasets, benchmark verification suites, and validation frameworks for AI-assisted EDA tools
Domain
Semiconductor EDA, AI-driven verification automation
Deliverable
production ML models
Required skills
SystemVerilog, UVM, RTL verification, functional coverage, assertion-based verification (SVA), constrained random methodologies, simulation debugging, formal verification, Python scripting, EDA tool integration
Preferred skills
AI/LLM familiarity, agentic AI systems, customer support experience, verification automation framework development
Technologies
Cadence Xcelium, Synopsys VCS, Siemens QuestaSim, Cadence JasperGold, Synopsys VC Formal, Shell, TCL
Responsibilities
Validate AI-generated UVM testbenches and assertions, debug complex customer verification issues, develop ground-truth benchmark datasets, collaborate with AI engineers to reduce model hallucinations, integrate AI systems with EDA workflows
Seniority
Senior, hands-on IC with domain expertise
