Mixed- Signal Systems and Verification Engineer
Core
Developing and verifying real-numbered behavioral models for analog/RF blocks in SystemVerilog to ensure accurate representation of analog schematics and integration with RTL.
Role type
Mixed-Signal Systems and Verification Engineer
Builds
Simulation-efficient analog behavioral models and verification environments for analog/RF blocks
Domain
Mixed-Signal / Analog / RF
Deliverable
production ML models | product features
Required skills
SystemVerilog, Verilog-AMS, RNM, UDN/UDT/UDR, wreal, Analog Assertion Based Verification, TB development, Perl scripting, Python scripting, Cadence Virtuoso Schematic Composer, Cadence ADE, low power Architecture, analog block knowledge (filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer)
Preferred skills
FPGA prototyping, DSP experience
Technologies
SystemVerilog, Verilog-AMS, Cadence Virtuoso, Cadence ADE, Perl, Python
Responsibilities
Develop accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog; Verify that behavior models are accurate representations of analog schematics; Integrate models with RTL; Verify analog functionalities against design specifications using analog behavioral models by coding test benches, test scenarios, and assertions; Document modeling and verification results for formal review
Seniority
Entry-level to Mid-level, hands-on IC