RTL2 GDS, Sr Principal AE
Core
Senior Application Engineer providing technical support and deployment guidance for Cadence's backend digital design implementation and signoff tools to semiconductor customers.
Role type
Sr Principal Application Engineer (Backend Digital Implementation & Signoff)
Builds
Production EDA flows for Place and Route, Design Closure, and timing/power signoff
Domain
Semiconductor / Electronic Design Automation (EDA)
Deliverable
client delivery
Required skills
Digital Design Fundamentals, Static Timing Analysis, Physical Design, Place and Route, IR Drop, backend design timing and power closure, advanced node design (10nm and below), scripting (Tcl/Perl/Python), customer-facing communication
Preferred skills
Front-end EDA tools (Synthesis, DFT, Logical Equivalence Checking), Cadence tool suite (Genus, Innovus, Conformal, Tempus, Modus, Voltus, ICC, DC, Primetime), advanced node design (5nm and below)
Technologies
Tcl, Perl, Python, Genus, Innovus, Conformal, Tempus, Modus, Voltus, ICC, DC, Primetime
Responsibilities
Provide technical support for backend digital design implementation and signoff, guide customers on tool utilization for design goals, conduct technical presentations and product demonstrations, drive technical evaluations and benchmarks, collaborate with R&D to enhance tools and methodologies, drive adoption of Cadence tools, provide guidance to amend design flows using scripting
Seniority
Sr Principal, hands-on IC with customer-facing leadership