Lead Physical Design Engineer
Core
Lead physical design engineer responsible for RTL synthesis to GDS implementation, optimization, and verification of IP, subsystems, or IC designs.
Role type
Senior IC physical design engineer (digital SoC/ASIC)
Builds
Digital integrated circuits (SoCs/ASICs) for semiconductor applications
Domain
Semiconductor / VLSI / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
floorplanning, placement, routing, clock tree synthesis, static timing analysis (STA), physical verification (DRC/LVS), power integrity analysis (IR drop/EM), DFT implementation, scripting (Tcl/Perl/Python), deep sub-micron process knowledge, VLSI design principles
Preferred skills
automation script development, physical design flow optimization, cross-functional collaboration
Technologies
Innovus, Cadence Genus/Tempus/Voltus/Pegasus, Mentor Calibre, Apache Redhawk
Responsibilities
Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA). Perform physical verification (DRC, LVS, Antenna) and resolve related issues. Conduct power integrity analysis (IR drop, EM) and optimize designs for power efficiency. Participate in design-for-test (DFT) implementation and verify test structures. Analyze and resolve design issues related to timing, area, and power. Develop and maintain scripts for automation and efficiency improvements in the physical design flow.
Seniority
Senior, hands-on IC