Lead Application Engineer - Design Verification
Core
Lead Application Engineer for Cadence SoC Verification, AI, simulation Emulation, and Acceleration products, focusing on customer technical evaluations, training, and solution scoping.
Role type
Senior IC Application Engineer (Design Verification)
Builds
Cadence SoC Verification solutions, AI solutions, simulation Emulation, and Acceleration products
Domain
Semiconductor EDA / Hardware Design Verification
Deliverable
client delivery
Required skills
Verilog/VHDL design, System Verilog/VHDL, HDL simulators, formal verification, UVM methodology, hardware emulator/accelerator experience, AI for design/verification, Japanese (business level)
Preferred skills
Jasper formal verification, advanced verification methodologies
Technologies
Verilog, VHDL, System Verilog, UVM, Jasper, HDL simulators, hardware emulators, accelerators
Responsibilities
Identify and scope opportunities for verification solutions with the Sales team; Plan and execute technical evaluations and benchmarks; Train and support customer projects; Conduct technical presentations and demos; Provide expert technical support for client queries; Align with engineering and sales teams on product direction based on customer requirements
Seniority
Senior, hands-on IC
