Design Verification Manager
Core
Driving SoC Design Verification (DV) and Analog Verification (AVnV) for high-growth markets including AI-driven data centers and humanoid systems.
Role type
Design Verification Manager
Builds
SoC solutions for AI data centers and humanoid systems
Domain
Semiconductor / Embedded Systems / AI Hardware
Deliverable
production ML models | product features
Required skills
SoC DV and AVnV (Pre/Post silicon, FPGA, Palladium), RTL and GLS regression, coverage goal tracking, design review facilitation, team mentorship, cross-functional collaboration, design verification methodology innovation, EDA tool flow management, silicon bring-up and debug support
Preferred skills
Power aware verification, GLS, AMS flows, stakeholder relationship building, rapid system ramp-up, analytical problem-solving, project delivery time management
Technologies
FPGA, Palladium, RTL, GLS, EDA tools
Responsibilities
Drive SoC DV and AVnV activities; Support verification/validation leads for power aware verification, GLS, AMS flows, Palladium and FPGA activities; Execute RTL and GLS regression and track coverage goals; Conduct design reviews; Mentor team members; Innovate and drive new design verification methodologies; Interact with Test/Silicon Validation/Application Engineering teams for product support and debug
Seniority
Senior, hands-on IC with mentorship responsibilities
