Sr Principal Application Engineer - Design Verification
Core
Sr Principal Application Engineer specializing in Design Verification, focusing on technical evaluations, customer training, and solution scoping for Cadence SoC Verification, AI, simulation, emulation, and acceleration products.
Role type
Sr Principal Application Engineer (Design Verification)
Builds
Cadence SoC Verification solutions, AI solutions, simulation emulation, and acceleration products
Domain
Semiconductor EDA (Electronic Design Automation)
Deliverable
client delivery
Required skills
Verilog/VHDL design, System Verilog/VHDL, HDL simulators, formal verification, UVM methodology, hardware emulator/accelerator experience, AI for design and verification
Preferred skills
Jasper experience, advanced verification methodology
Technologies
Verilog, VHDL, System Verilog, Jasper, UVM
Responsibilities
Identify and scope opportunities for verification solutions with the Sales team; Plan, execute, and manage technical evaluations and benchmarks; Train and accompany customer projects; Conduct technical trainings, presentations, and demos; Provide expert technical support for client queries; Align with engineering and sales/marketing on product direction based on customer requirements
Seniority
Senior, hands-on IC with strategic client engagement
