Sr. Principal Software Engineer
Core
Design and implement advanced Design-for-Test (DFT) hardware, test fabrics, and on-chip test networks for next-generation SoCs.
Role type
Sr. Principal Hardware Engineer (DFT)
Builds
DFT IP, scan compression, LBIST, MBIST, POST, IST, and test access architectures for semiconductor SoCs
Domain
Semiconductor EDA / Design-for-Test (DFT)
Deliverable
production ML models
Required skills
RTL Design & Verification, Verilog/SystemVerilog, UVM, DFT Architecture, SoC Integration, Synthesis & Timing Closure, IP Development, Debugging
Preferred skills
ISO 26262 functional safety, security-aware hardware design, automotive/industrial/AI IP development, Cadence tool flows (Xcelium, JasperGold, etc.)
Technologies
Verilog, SystemVerilog, Perl, Python, UVM, Xcelium, JasperGold, Genus, Innovus, Tempus, Modus (via careerplan.io/jobs/R54782-sr-principal-software-engineer-at-cadence)
Responsibilities
Design DFT hardware and test fabrics, develop reusable IPs from architecture to delivery, manage IP integrations, debug complex hardware issues, lead design/architecture reviews, mentor engineers
Seniority
Sr. Principal, technical leadership & mentorship
