Sr. Principal Product Engineer – Digital & Signoff Group (DSG)
Core
Act as a bridge between R&D, Application Engineering, and global customers to influence the next generation of chip design software, solving complex physical design challenges at 7nm and below.
Role type
Sr. Principal Product Engineer (Physical Design & Signoff)
Builds
Chip design software tools and methodologies for the semiconductor industry
Domain
Semiconductor EDA / Physical Design
Deliverable
product features
Required skills
ASIC design flow (RTL-to-GDSII), physical design, timing analysis, PPA optimization, 7nm/5nm node experience, EDA tools (synthesis, placement, routing, signoff), Tcl, Python, Perl
Preferred skills
AI-driven productivity tools
Responsibilities
Serve as primary place-and-route (P&R) resource for internal teams and external customers; collaborate with R&D to track, diagnose, and resolve software issues; execute competitive benchmarks for Power, Performance, and Area (PPA); develop and deploy customized RTL-to-GDSII methodologies and scripts; partner with Product Marketing to align technical capabilities with market needs.
Seniority
Sr. Principal, hands-on IC
