Application Engineer Manager – Formal Verification and Functional Simulation
Core
Lead customer success initiatives for Digital, Analog, Verification, and Systems tools by solving complex verification issues and driving product improvements.
Role type
Manager, Application Engineering (Formal Verification & Functional Simulation)
Builds
Customer verification productivity and tool adoption for semiconductor design flows
Domain
Semiconductor EDA / Electronic Design Automation
Deliverable
client delivery
Required skills
Formal Verification (Jasper, FPV, CDC), Functional Simulation (Xcelium, UVM), verification sign-off criteria, root cause analysis, team leadership, technical content creation, account strategy
Preferred skills
Scripting (Tcl, Python, Perl), ML/AI-assisted verification, mentoring engineers
Technologies
Jasper, FPV, Xcelium, UVM, Tcl, Python, Perl
Responsibilities
Debug complex verification issues for customers, guide verification strategies and methodologies, create technical content and best-practice documents, mentor engineers, partner with Sales on account strategies, deploy ML/AI verification solutions, analyze root causes of customer problems
Seniority
Manager, hands-on technical leadership
