Digital Verification Engineer
Core
Ensure digital and mixed-signal products behave exactly as specified before silicon using Metric Driven Verification (MDV) flow.
Role type
Digital Verification Engineer (IC/SoC)
Builds
Mixed-signal ICs, large-scale SoCs with embedded processors, hardware-software co-designed products
Domain
Semiconductor, Intelligent Edge, AI-augmented engineering
Deliverable
production ML models | product features
Required skills
Digital logic design, SystemVerilog, UVM, C++, simulation-based verification, formal verification, FPGA validation, bus protocols (AXI/AHB/APB), AI tool review
Preferred skills
Python, Perl, Tcl, AI/ML for edge deployment, SVA, coverage closure, DSP/audio systems, high-speed connectivity, closed-loop control, analog/mixed-signal co-simulation
Technologies
SystemVerilog, UVM, C++, Python, Perl, Tcl, FPGA, AI coding assistants
Responsibilities
Analyze specifications to define verification scope and coverage goals; Build and maintain block- and system-level testbenches; Create test cases and drive functional/coverage closure; Investigate failures across RTL and system boundaries; Apply agentic AI tools to accelerate verification tasks
Seniority
Graduate / Entry-level
