Analog Design Engineer
Core
Design and develop next-generation SerDes and wireline communication systems, including high-speed analog and mixed-signal building blocks.
Role type
Analog Design Engineer (SerDes)
Builds
High-speed analog and mixed-signal building blocks for multi-gigabit data links
Domain
Semiconductor / High-Speed Connectivity
Deliverable
production ML models | product features
Required skills
Analog and mixed-signal fundamentals, CMOS circuit design, SerDes fundamentals, circuit simulation and modeling, programming and automation, AI tool understanding and usage, AI output validation
Preferred skills
Deep experience designing SerDes building blocks (ADC, DAC, TX/RX, PLL, CDR, CTLE, DFE), high-speed circuit design experience above 10 GS/s, tape-out and silicon validation experience, knowledge of wireline communication standards, Python or MATLAB proficiency
Technologies
Cadence Virtuoso, SPICE, Spectre, MATLAB, Simulink, Python
Responsibilities
Design and analyze high-speed analog and mixed-signal circuit blocks, perform block-level and transistor-level simulations, contribute to SerDes building block development, optimize performance/power/area, collaborate on layout and post-layout verification, support silicon bring-up and debugging, cross-functional collaboration on system-level objectives
Seniority
Entry-level (Graduate)