Associate Design Verification Engineer
Core
Develop test benches and perform design verification for new digital, analog, and mixed-signal products prior to tape-out.
Role type
Associate Design Verification Engineer
Builds
Mixed-signal products
Domain
Semiconductor / Analog & Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Verilog RTL, Python/Perl/TCL scripting, I2C/SPI/UART protocols, simulation debugging
Preferred skills
None stated
Technologies
SystemVerilog, UVM, Python, Perl, TCL, Verilog
Responsibilities
Develop and execute basic test benches for mixed-signal product verification, Create and maintain basic test environments using SystemVerilog/UVM, Conduct code coverage analysis to ensure design accuracy, Debug simulation failures and track coverage metrics, Support verification planning and documentation, Collaborate with design teams to understand requirements
Seniority
Entry-level, 0-2 years experience