Senior Engineer, Digital Design Engineering
Core
Create, enhance, and maintain SystemVerilog/UVM verification environments, checkers, scoreboards, assertions, and functional coverage models for SoC verification.
Role type
Senior IC digital design verification engineer
Builds
Verification environments, testbenches, and formal verification setups for semiconductor SoCs
Domain
Semiconductor / Digital Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: production ML models is wrong, this is verification environments)
Deliverable
verification environments and testbenches
Required skills
SystemVerilog, SVA, UVM, constrained-random verification, formal property verification (FPV), C/C++ for firmware testing, Python/Tcl scripting, SoC interface knowledge (AMBA AHB/APB/AXI)
Preferred skills
Commercial protocol VIP integration, AI-assisted engineering tools, ARM Cortex-M processor verification, emulation or FPGA prototyping, non-volatile memory verification
Technologies
SystemVerilog, UVM, Python, Tcl, Shell, Perforce, Git, Cadence VIPs, Synopsys VIP
Responsibilities
Develop comprehensive verification plans and metric-driven closure; Architect formal verification environments from scratch; Write SVA assertions for protocol compliance; Integrate protocol VIPs within verification environments; Collaborate with designers on cross-block verification; Support emulation, firmware integration, and post-silicon validation
Seniority
Senior, hands-on IC
