Lead EDA Engineer
Core
Lead backend physical verification strategy and design enablement for analog and mixed-signal teams across multiple programs and advanced process nodes.
Role type
Lead EDA Engineer (Physical Verification)
Builds
Calibre-based verification flows, signoff readiness infrastructure, and internal automation tools for tapeout execution.
Domain
Semiconductor / Analog & Mixed-Signal IC Design / Physical Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical verification (DRC, LVS, ERC, PERC, extraction), Mentor Calibre (SVRF, TVF), advanced node foundry rules (TSMC 16nm/5nm/4nm), Python/Tcl/Shell scripting, Linux EDA environments, analog layout understanding
Preferred skills
Digital physical design/PR verification, Perforce, Cadence Virtuoso (SKILL), EDA license management, GUI tool development, AI-assisted engineering methods
Technologies
Mentor Calibre, TSMC, Python, Tcl, Shell, Linux, Perforce, Cadence Virtuoso
Responsibilities
Define and evolve Calibre-based verification flows; lead resolution of complex runset and rule deck issues; drive foundry rule intake and integration; own tapeout readiness and waiver governance; build internal automation and dashboards; shape multi-site EDA infrastructure; mentor engineers on verification methodologies
Seniority
Senior, hands-on IC