Principal Digital Design Engineer
Core
Lead digital RTL development and architecture for complex digital controllers in power management ICs (PMICs) and mixed-signal ICs using FinFast™ technology.
Role type
Principal Digital Design Engineer (SoC/PMIC)
Builds
Ultra-compact, ultra-efficient digital controllers for power management ICs
Domain
Semiconductor / Power Management ICs / Digital Design
Deliverable
production ML models | product features
Required skills
RTL design, finite state machines, digital architecture for embedded/mixed-signal, synthesis tools (Synopsys, Cadence), digital design flow (simulation, timing constraints, STA), debugging, asynchronous digital design, embedded-cores
Preferred skills
Analog and full custom circuit design understanding
Technologies
FinFast™, Synopsys, Cadence, Xcelium, PMBus, AVSbus, I2C/SPI, PCMI
Responsibilities
Define top-level requirements and specifications for digital functions; design, implement, and integrate digital blocks including control loops, state machines, multi-bus systems, embedded cores, and clock-trees; own and write synthesizable RTL; collaborate with AMS/DV teams for integration and simulation; execute synthesis, linting, CDC/STA checks, and backend support.
Seniority
Principal, strategy & mentorship
