Senior Design Verification Engineer
Core
Lead verification planning and execution for complex digital and mixed-signal semiconductor designs, architecting advanced verification environments and driving post-silicon validation.
Role type
Senior IC design verification engineer (mixed-signal/digital)
Builds
High-reliability mixed-signal and digital IC products for the Intelligent Edge
Domain
Semiconductor / Mixed-signal and digital integrated circuits
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, mixed-signal design principles, constrained random verification, assertion-based verification, Python scripting, Perl scripting, TCL scripting, functional coverage analysis, debug leadership
Preferred skills
Master's degree in Electrical or Computer Engineering, 4-8 years of IC verification experience
Technologies
SystemVerilog, UVM, Python, Perl, TCL
Responsibilities
Architect comprehensive verification strategies for complex designs, develop advanced UVM-based verification environments, establish and oversee code and functional coverage metrics, lead debug efforts for complex design issues, provide technical mentorship to junior engineers, collaborate with design teams on verification planning, lead silicon bring-up and post-silicon validation activities
Seniority
Senior, hands-on IC with mentorship responsibilities
