Senior Manager, Design Verification Engineering
Core
Lead design verification efforts for complex digital designs and subsystems across the entire product lifecycle, from concept to release, while managing a large team of DV engineers.
Role type
Senior Manager, Design Verification Engineering
Builds
IP components and subsystems for various product teams within Analog Devices
Domain
Semiconductor / ASIC Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC design verification, team management (20+ people), verification strategy definition, constrained-random verification, functional and code coverage, assertion-based methodology, formal verification, analog behavioral modeling, SystemVerilog real-number modeling, mixed-signal simulation, AI tools for verification, processor-based verification, gate-level simulation, Verilog, C/C++, SystemC, Java, TCL, Perl, Python, shell scripting, PSL, MATLAB, digital signal processing, low-power methodologies (CPF, UPF)
Preferred skills
digital signal processing, low-power methodologies (CPF, UPF)
Responsibilities
Verify complex digital designs and sub-systems using leading edge verification methodologies; Manage and mentor a high performing team of DV engineers, plan the DV strategy, manage the execution; Define verification strategy, test plans, tests and verification methodology for chip-level verification; Interact with various BU teams to understand SoC use cases and enhance DV; Work with design teams to generate test-plans and closure of code and functional coverage; Track and manage design verification improvements
Seniority
Senior Manager, strategic leadership & hands-on IC