Senior Engineer, Design Verification Engineering
Core
Senior Design Verification Engineer supporting product development of industry-leading analog, digital, and mixed-signal ICs through behavioral modeling, full-chip verification, and simulation infrastructure.
Role type
Senior IC Design Verification Engineer
Builds
System Verilog simulation environments, verification infrastructure, and full-chip simulation models for analog and digital circuits.
Domain
Semiconductor / Analog and Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Perl scripting, Python scripting, Cadence Xcelium, Synopsys VCS, coverage analysis, mixed-signal verification, analog circuit understanding, digital circuit understanding
Preferred skills
metric-driven verification methodologies, verification planning, test bench architecture, system debugging
Technologies
System Verilog, UVM, Cadence Xcelium, Synopsys VCS, Perl, Python
Responsibilities
Create System Verilog simulation environments and infrastructure to verify functionality, accuracy, and performance; correlate verification results with multidisciplinary design teams; support design teams in identifying, debugging, and resolving issues; develop project verification strategies and perform results analysis.
Seniority
Senior, hands-on IC
