Senior Engineer, Design Verification Engineering
Core
Develop and own verification for key digital blocks in mixed-signal SOCs for consumer audio products like hearables and prosumer audio.
Role type
Senior IC design verification engineer (UVM, SoC)
Builds
Mixed-signal System-on-Chips (SoCs) for consumer audio markets
Domain
Semiconductor / Consumer Electronics / Audio
Deliverable
production ML models | product features
Required skills
UVM testbench development, functional coverage closure, code coverage analysis, assertion development, IP and SoC level verification, gate-level simulation, scripting (Python, Perl, Makefile), mixed-signal SoC integration, post-silicon silicon bring-up, ATE pattern bring-up
Preferred skills
AHB/AXI/APB protocols, power-aware simulations, formal verification, digital signal processing (MATLAB/Octave), HW emulation, FPGA prototyping, ML techniques for verification
Technologies
UVM, Python, Perl, Makefile, MATLAB, Octave, AHB, AXI, APB
Responsibilities
Develop UVM-based testbench infrastructure from ground up; achieve functional and code coverage closure; debug and articulate gating issues; integrate block-level testbenches at SOC level; support post-silicon activities including silicon bring-up and ATE pattern bring-up
Seniority
Senior, hands-on IC