Senior Engineer, Design Verification Engineering
Core
Senior Design Verification Engineer creating self-checking test benches and simulation environments to validate analog, digital, and mixed-signal IC designs before production.
Role type
Senior IC Design Verification Engineer
Builds
Production-ready mixed-signal and digital ICs for the Intelligent Edge
Domain
Semiconductor / Mixed-Signal IC Design
Deliverable
production ML models | product features
Required skills
System Verilog, UVM, Perl scripting, Python scripting, Cadence Xcelium, Synopsys VCS, coverage analysis, mixed-signal circuit knowledge, digital circuit knowledge, simulation infrastructure design, test bench architecture, debugging complex circuits
Preferred skills
metric-driven verification methodologies, full-chip verification strategies, multidisciplinary team collaboration
Technologies
System Verilog, UVM, Cadence Xcelium, Synopsys VCS, Perl, Python
Responsibilities
Create self-checking test benches to validate designs; develop System Verilog simulation environments and infrastructure; correlate simulation results with multidisciplinary design teams; identify, debug, and resolve design issues; assist in developing project verification strategies and resource tracking
Seniority
Senior, hands-on IC
