PD Director
Core
Lead end-to-end physical implementation of complex, high-performance SoCs on leading-edge process nodes, ensuring optimal PPA and first-pass silicon success.
Role type
Senior IC Physical Design Director
Builds
Complex SoCs integrating multiple processor cores and high-performance signal processing hardware
Domain
Semiconductor / Advanced Node Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: physical/clinical work -> infrastructure/SoC)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (SoC designs)
Required skills
End-to-end RTL-to-GDSII execution, Timing Signoff (STA), Power Signoff (SI, IR/EM), Floorplanning, Placement & Routing, Clock Architecture/CTS, DRC/LVS closure, PPA optimization, Low-power design (UPF/CPF), Automation scripting (TCL, Python, Perl), Cross-functional leadership
Preferred skills
Experience with 22nm/16nm/5nm/3nm nodes, Library strategy, Congestion management, ECO flow optimization
Technologies
22nm, 16nm, 5nm, 3nm, 28nm, 10nm, STA, SI, IR/EM, UPF/CPF, TCL, Python, Perl
Responsibilities
Directed end-to-end RTL-to-GDSII execution across multiple SoC programs; Owned timing, power, and physical signoff strategy; Drove PPA optimization through congestion management and library strategy; Established DRC/LVS closure methodologies; Partnered with RTL, DFT, packaging, and system teams; Built and scaled high-performing physical design teams; Defined automated design methodologies; Delivered high-complexity designs on advanced nodes; Championed low-power design strategies
Seniority
Director, hands-on IC with leadership