Principal Engineer, Digital Verification Engineering
Core
Own verification strategy and closure for complex analog and mixed-signal ICs, driving AI/ML adoption to improve regression efficiency and coverage.
Role type
Principal Design Verification Engineer (Mixed-Signal/Analog)
Builds
Reusable SystemVerilog/UVM testbenches, monitors, scoreboards, automated checkers, and AI/ML-driven verification workflows
Domain
Semiconductor / Mixed-Signal IC Design / AI for Verification
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, Python scripting, AI/ML techniques, formal verification, assertion-based methodology, clock domain crossing analysis, mixed-signal verification, coverage planning, tape-out sign-off
Preferred skills
Verilog-AMS, real-number modeling, gate-level simulation, SDF back-annotation, post-layout verification, power management verification
Technologies
Xcelium, JasperGold, SystemVerilog, UVM, Python
Responsibilities
Drive adoption of AI/ML methodologies for failure clustering, regression triage, anomaly detection, and intelligent coverage optimization; Define and own verification strategy, plans, and success metrics across block, top-level, and system contexts; Build and scale mixed-signal verification infrastructure; Lead functional coverage planning, closure analysis, and sign-off; Drive silicon correlation by comparing simulation expectations against lab measurements; Lead verification architecture and methodology reviews
Seniority
Principal, strategy & mentorship