Principal Design Verification Engineer
Core
Architect sophisticated verification environments and define verification strategies for complex analog and mixed-signal semiconductor designs.
Role type
Principal Design Verification Engineer (Strategic IC)
Builds
Verification environments and methodologies for analog/mixed-signal chips
Domain
Semiconductor / Analog & Mixed-Signal Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (verification environments)
Required skills
SystemVerilog, UVM, Mixed-signal verification, Advanced debugging, Verification strategy architecture, Technical leadership, Strategic problem solving
Preferred skills
Team leadership, Standards development, Tool vendor collaboration
Technologies
SystemVerilog, UVM
Responsibilities
Define verification strategy and architecture for complex designs, Pioneer advanced verification methodologies, Drive verification decisions across organizational lines, Lead resolution of challenging verification issues, Mentor verification engineers at all levels, Represent company at industry forums and with key customers, Establish verification metrics and quality standards
Seniority
Principal, strategic influence & mentorship