Staff Design Verification Engineering
Core
Define and develop block/top-level verification strategies for complex mixed/digital signal ICs, including digital signal processing data-paths, sensors, and high-speed interfaces.
Role type
Staff Analog and Mixed Signal (AMS) Verification Engineer
Builds
Signal Chain solutions for Industrial applications
Domain
Semiconductor / Analog and Mixed Signal ICs
Deliverable
production ML models | product features
Required skills
Analog and Mixed Signal verification, System Verilog, UVM, constrained random verification, functional coverage, assertions, formal verification, gate-level simulation, mixed-signal co-simulation, circuit design understanding, system-level architecture, scripting (Python, TCL, Perl, Bash), analog checker development
Preferred skills
Technical mentoring and coaching junior engineers, expertise in Mixed Signal Simulations
Technologies
Cadence Virtuoso, Xcelium, Verilog, Spice simulators
Responsibilities
Define verification plans and environments from scratch; develop analog checkers, SV assertions, and functional coverage; perform RTL, gate, and mixed-signal co-simulation regressions; debug designs and environments with designers; compare simulation results with silicon evaluation; mentor junior engineers; improve verification flow and methodology
Seniority
Senior, hands-on IC