Engineer, Physical Design Engineering
Core
Own end-to-end physical implementation for major IP blocks and/or full-chip designs, ensuring alignment with ADI's Career Development Framework.
Role type
Senior IC physical design engineer (ASIC/SoC)
Builds
ASIC/SoC chips at advanced nodes (40nm to 16nm)
Domain
Semiconductor / Analog & Mixed-Signal
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
floorplanning, place-and-route, clock tree synthesis, static timing analysis (STA), physical verification (DRC/LVS/ERC), automated design flows (Tcl/Perl/Python), PPA optimization, process-aware design
Preferred skills
hierarchical design, large-scale SoC integration, low power design (UPF/CPF)
Technologies
Cadence Innovus, Tcl, Perl, Python
Responsibilities
Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis); Execute place-and-route, clock tree synthesis, and timing closure; Perform detailed static timing analysis (STA) and drive sign-off across PVT corners; Identify and resolve physical verification issues (DRC/LVS/ERC); Automate design flows to improve efficiency; Mentor and coach junior engineers; Document methodologies and contribute to best practices
Seniority
Senior, hands-on IC