Staff Digital Verification Engineer
Core
Develop and execute verification plans for complex digital and mixed-signal IPs and subsystems to ensure high product quality and first-pass silicon success.
Role type
Staff Digital Design Verification Engineer
Builds
Digital and mixed-signal IPs, subsystems, and top-level designs for semiconductor solutions
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, constrained-random testing, coverage-driven verification, formal verification, gate-level simulation, timing checks, low-power verification, DFT/scan verification, ATPG, RTL design collaboration
Preferred skills
Perl, Python, TCL scripting, mixed-signal or AMS verification experience
Technologies
SystemVerilog, UVM, Perl, Python, TCL
Responsibilities
Develop verification plans and strategies; Build SystemVerilog/UVM testbenches with reusable components; Implement constrained-random and coverage-driven test scenarios; Achieve functional and assertion coverage targets; Apply formal verification and integrate assertions; Collaborate with RTL designers to debug issues; Perform gate-level simulations and timing checks; Verify integration of digital interfaces (SPI, I2C, UART, JTAG); Contribute to DFT/scan verification and ATPG; Support post-silicon bring-up; Document verification environments and methodologies
Seniority
Senior, hands-on IC
